MAX5965AEAX+【PDF 46/54 页】IC PSE CTRLR FOR POE 36SSOP

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Sheet目录43

42页 43页 44页 45页 [46页]47页 48页 49页 50页

High-Power, Quad, Monolithic, PSE Controllers

for Power over Ethernet

46 ______________________________________________________________________________________

ADDR

R/W PORT

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RESET

STATE

MAXIM RESERVED

20h

Reserved

21h

Reserved

22h

Reserved

23h

Program

R/W

4321

Reserved

CLC_EN

DET_BY

OSCF_RS

AC_TH[2]

AC_TH[1]

AC_TH[0]

24h

High-Power Mode

R/W

Reserved

HP[2]

HP[1]

HP[0]

Reserved

0000,0000

25h

Reserved

0000,0000

26h

Reserved

0000,0000

27h

Reserved

28h

Reserved

29h

Miscellaneous

Configuration 2

R/W

1234

Reserved

LSC_EN

IVEE[1]

IVEE[0]

0000,0000

2Ah

ICU T Regi ster

s 1 and 2 R/W

Reserved

ICUT2[2]

ICUT2[1]

ICUT2[0]

Reserved

ICUT1[2]

ICUT1[1]

ICUT1[0]

0000,0000

2Bh

ICU T Regi ster

s 3 and 4 R/W

Reserved

ICUT4[2]

ICUT4[1]

ICUT4[0]

Reserved

ICUT3[2]

ICUT3[1]

ICUT3[0]

0000,0000

CLASSIFICATION STATUS REGISTERS

2Ch

Port 1 Class

Reserved

CLS1[5]

CLS1[4]

CLS1[3]

CLS1[2]

CLS1[1]

CLS1[0]

0000,0000

2Dh

Port 2 Class

Reserved

CLS2[5]

CLS2[4]

CLS2[3]

CLS2[2]

CLS2[1]

CLS2[0]

0000,0000

2Eh

Port 3 Class

Reserved

CLS3[5]

CLS3[4]

CLS3[3]

CLS3[2]

CLS3[1]

CLS3[0]

0000,0000

2Fh

Port 4 Class

Reserved

CLS4[5]

CLS4[4]

CLS4[3]

CLS4[2]

CLS4[1]

CLS4[0]

0000,0000

CURRENT REGISTER

30h

Current Port 1 (MSB)

IPD1[8]

IPD1[7]

IPD1[6]

IPD1[5]

IPD1[4]

IPD1[3]

IPD1[2]

IPD1[1]

0000,0000

31h

Current Port 1 (LSB)

Reserved

IPD1[0]

0000,0000

32h

Current Port 2 (MSB)

IPD2[8]

IPD2[7]

IPD2[6]

IPD2[5]

IPD2[4]

IPD2[3]

IPD2[2]

IPD2[1]

0000,0000

33h

Current Port 2 (LSB)

Reserved

IPD2[0]

0000,0000

34h

Current Port 3 (MSB)

IPD3[8]

IPD3[7]

IPD3[6]

IPD3[5]

IPD3[4]

IPD3[3]

IPD3[2]

IPD3[1]

0000,0000

35h

Current Port 3 (LSB)

Reserved

IPD3[0]

0000,0000

36h

Current Port 4 (MSB)

IPD4[8]

IPD4[7]

IPD4[6]

IPD4[5]

IPD4[4]

IPD4[3]

IPD4[2]

IPD4[1]

0000,0000

37h

Current Port 4 (LSB)

Reserved

IPD4[0]

0000,0000

Table 35. Register Summary (continued)

*UV and UVLO bits of V

and V

asserted depends on the order V

and V

supplies are brought up.

A = AUTO pin state before reset.

M = MIDSPAN state before reset.

A3...0 = ADDRESS input states before reset.

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